Field of the Invention
The present disclosure relates to semiconductor package, and more particularly, to a package assembly and methods for manufacturing the same.
Description of the Related Art
With an increasing demand for miniaturization, light weight and multifunctionality of electronic devices, a semiconductor package is developed towards a high packaging density so that a package size can be reduced. A package assembly using a leadframe and encapsulating a plurality of semiconductor chips has attracted attention. In such package assembly, configuration of the semiconductor chips and their connections have significant effects on the package size and properties of the package assembly.
FIG. 1 is a perspective view showing a conventional multi-chip package assembly 100. In the package assembly 100, two semiconductor chips 120 and 130 are arranged side by side on a leadframe 110. The leadframe 110 includes a plurality of finger-like leads 111. Each lead 111 has a top surface with a contact pad 112. Conductive bumps 121 are provided at a lower surface of the first semiconductor chip 120, and are soldered to respective ones of the contact pads 112 of a first group of leads 111. Conductive bumps 131 are provided at a lower surface of the second semiconductor chip 130, and are soldered to respective ones of the contact pads 112 of a second group of leads 111. The leadframe 110 and the semiconductor chips 120 and 130 are encapsulated by an encapsulant layer 160. At least portions of the leads 111 of the leadframe 110 are exposed from the encapsulant layer 160, for electric connection with external circuits, such as a PCB (i.e. printed circuit board).
Nevertheless, the arrangement of the semiconductor chips 120 and 130 side by side is disadvantageous in terms of the packaging density, because the resultant package assembly 100 occupies an area larger than a sum of footprints of the semiconductor chips 120 and 130.
On the other hand, a stacked package assembly is also proposed, in which a plurality of semiconductor chips are stacked on a leadframe. Semiconductor chips in the lowermost level are secured on a leadframe by soldering. Semiconductor chips in an upper level may be secured by adhesion on top surfaces of semiconductor chips in a lower level. The semiconductor chips in the upper level may be electrically coupled to the leadframe by bonding wires. Although the stacked package assembly can reduce its footprints, the bonding wires are used in the package assembly and result in a complex bonding process and an increased manufacture cost.
In the above stacked package assembly according to the prior art, a large number of bonding wires are used and possibly interference with each other, which deteriorates high-frequency performance of the semiconductor devices in the package assembly, or even failure of the electronic devices in the package assembly due to poor electrical contact of the bonding wires. In a case that the package assembly includes an inductor electrically coupled to other electronic devices in the package assembly through an external conductive path, the external conductive path will introduce noise.
Thus, it is desirable that the packaging density of the package assembly be increased while its reliability and electrical performance be improved.